In Development
Mac SE PDS (96-pin Euro-DIN)
|
v
+-------------------------------+
| Bus Interface CPLD |
| Lattice MachXO2-2000HC |
| |
| - Address decoding |
| - Wait state generation |
| - Clock domain crossing |
| (8 MHz SE <-> 25-50 MHz) |
+---------------+---------------+
|
v
+-------------------------------+
| MC68030 @ 25-50 MHz |
| + MC68882 FPU |
| |
| - Full 32-bit address/data |
| - On-chip MMU |
+---------------+---------------+
|
v
+-------------------------------+
| 64 MB SDRAM |
| IS42S16320F x2 |
| 32-bit data path, burst mode |
+-------------------------------+
|
v (optional)
+-------------------------------+
| WIZnet W5500 Ethernet |
| 10/100 Mbps |
| Hardware TCP/IP stack |
+-------------------------------+
The Problem
The Macintosh SE has one PDS slot. Today you must choose between a CPU accelerator, extra RAM, or networking. You can't have all three.
The Solution
One card that does it all: a 68030 CPU upgrade, 64 MB of fast SDRAM, and optional Ethernet — on a single PDS card. No more painful trade-offs.
Key Specs
| CPU | MC68030 @ 25–50 MHz with on-chip MMU |
|---|
| FPU | MC68882 (matched clock) |
|---|
| RAM | 64 MB SDRAM (32-bit data path, burst mode) |
|---|
| Bus Logic | Lattice MachXO2-2000HC CPLD |
|---|
| Ethernet | WIZnet W5500 (optional, 10/100 Mbps) |
|---|
| Interface | 96-pin Euro-DIN (Mac SE PDS) |
|---|
| PCB | 4-layer, JLCPCB fabrication |
|---|
| License | CERN OHL v2 (open source) |
|---|
What This Enables
- Run System 7.5.x properly with 32-bit addressing and virtual memory
- Real applications: Photoshop, ClarisWorks, compilers — without swapping
- Full networking without sacrificing CPU speed
- FPU support for CAD, rendering, and scientific software
- Transforms the SE from a novelty into a usable System 7 workstation
Estimated BOM
| Component | Est. Cost |
|---|
| MC68030RC50 CPU | $80–150 |
| MC68882RC50 FPU | $10–20 |
| MachXO2-2000HC CPLD | $8 |
| 64 MB SDRAM (×2 ICs) | $6 |
| W5500 Ethernet (optional) | $3 |
| 96-pin DIN connector + PCB | $15–25 |
| Estimated Total | ~$130–220 |
|---|
Timeline
This card is in the design and research phase. Development is happening in the open — follow along on Forgejo.
- Phase 1: Bus interface validation — PDS breakout board, signal timing
- Phase 2: CPU takeover — bus arbitration, clock domain crossing
- Phase 3: RAM expansion — SDRAM controller, 32-bit addressing
- Phase 4: Ethernet and peripherals
- Phase 5: Production and open-source release
Email rob@sadmacs.com to get notified when updates are available.
